In current fabrication processes for semiconductor devices according to VLSI or ULSI technology, one of the most important reliability problems is to preserve the integrity of the dielectric characteristic of thin oxide layers during treatment of the wafers. Thin oxide layers include gate oxides and interpoly dielectrics, for example. The criticality of this requirement is increasingly more important because of the technological advances that imply a continuous reduction or scaling down of the thickness of functional dielectric films. For example, a gate oxide thickness on the order of 5 nm or less are commonly used.
Many process steps may potentially degrade or damage the dielectric characteristic of such functionally active oxides. However, it is well known that among the most damaging conditions under this profile are those that occur during dry etching in a plasma when patterning the first levels of metallization. Another such condition is at the beginning of the exposure of the wafer to the plasma when depositing isolation layers using plasma enhanced chemical vapor deposition (PECVD), for example.
Some of the structural features of electrically conducting material on the surface of the wafer are directly exposed to the plasma. These structural features are customarily placed on a plate electrode or platen of the reactor that cooperates with another electrode in causing ionization of a gaseous mixture introduced in the evacuated chamber by injecting radio frequency (RF) signals to electrically charge the structural features. Consequently, these structures act as antennas and are electrically charged.
The electric path may include the electric charge of an active dielectric film, such as a gate oxide or an interpoly dielectric. The strong electric field that is induced on the dielectric may damage it due to a breakdown voltage across the wafer substrate and the electrode on which the wafer is placed. The effects of breakdown currents through thin gate or interpoly isolation dielectrics may irreversibly degrade the dielectric properties. To limit below an empirically determined value the electric stress that may be induced in the dielectric, appropriate design approaches are implemented.
These practices are based on checking the RF energy conditions. For example, this may be done by limiting the ratio between the exposed area of the conducting material on the wafer surface (antenna) and the coupling area with the dielectric layer to limit the total amount of electric charge that may be accumulated. These practices are not easily adaptable to changing process conditions.
Another widely used approach, where it is difficult or unpractical to assure safe conditions, includes forming dedicated protective diodes in parallel with the dielectric to be protected. These protective diodes are placed between the exposed conductor and the semiconductor substrate to provide a discharge path from the conductor material exposed to the plasma and the substrate, and vice-versa. This type of protection is effective when the junction (protecting diode) is directly biased, but may be insufficient when the difference of potential caused by the charging of the exposed conductor reverse biases the protecting diode. This reverse biasing condition for a gate dielectric is inevitable since the protecting diode must not effect normal operating conditions of the finishing product.
In case of gates directly connected to input pins of the device, the protecting diodes will continue to function as a protection device from accidental electrostatic discharges that may hit the pin while handling the device. The protection diodes are typically N+/P or P+/N diodes, or Zener diodes. FIGS. 1 and 2 show a typical arrangement of Zener diodes for protecting the gate dielectric of a CMOS inverter.
The Zener voltage must suit the designed supply voltage of the circuit and the peculiar electrical properties of the structure to be protected. Two or more Zener diodes in series may be used to provide greater flexibility in defining the range of allowed potentials. In the two examples shown, the metal line M represents a first metal level line or a polysilicon gate line.
FIG. 3 shows a cross-section of a semiconductor device during the fabrication process and, more particularly, at the stage when a first metal level is being patterned by masking. The first metal level follows the formation of the gate structures of the devices by patterning a G layer of polysilicon.
During the plasma etching which patterns the metal layer M, the charging path of a gate dielectric passes through the interconnection or via V between the polysilicon G and the metal layer M. The gate dielectric is protected by forming an N+/P substrate junction and by connecting it through a contact P to the conductor layer M. A similar protecting diode is also shown in the right side portion of the figure.
FIG. 4 shows another arrangement for protecting against an excessive charging of the gate polysilicon G by forming Zener junction between the P+ and N+ regions. The contact towards the substrate is formed through the P contact and the P+ diffusion, as shown at the leftmost portion of the cross-sectional view.
The constant technological advances in the fabrication processes for scaling down integrated structures makes it ever more difficult to ensure sufficient protection of dielectric layers as they become thinner, and thus more delicate in terms of preserving their optimal dielectric properties. In these circumstances, the distribution and the structure of the protective junctions become more critical.